EP82562ET Datasheet, PDF (27/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562ET
5.3.3
5.3.4
5.3.5
5.3.6
Bit(s)
Name
2
Extended
Squelch
1
Link Integrity
Disable
0
Jabber Function
Disable
Description
1 = 10BASE-T Extended Squelch control enabled
0 = 10BASE-T Extended Squelch control disabled
0 = Normal Link Integrity operation
1 = Link disabled
0 = Normal Jabber operation
1 = Jabber disabled
Default
0
R/W
RW
0
RW
0
RW
Register 18: PHY Address Register
Bit(s)
Name
15:5 Reserved
4:0
PHY Address
Description
These bits are reserved and should be set to a
constant 0.
These bits are set to the PHY’s address.
Default
0
R/W
RO
00001 RO
Register 19: 100BASE-TX Receive False Carrier Counter Bit
Definitions
Bit(s)
Name
15:0 Receive False
Carrier
Description
These bits are used for the false carrier counter.
Default
--
R/W
RO
SC
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
Bit(s)
Name
Description
15:0 Disconnect Event This field contains a 16-bit counter that increments for
each disconnect event. The counter stops when it is
full and self-clears on read
Default
--
R/W
RO
SC
Register 21: 100BASE-TX Receive Error Frame Counter Bit
Definitions
Bit(s)
Name
15:0 Receive Error
Frame
Description
This field contains a 16-bit counter that increments
once per frame for any receive error condition (such
as a symbol error or premature end of frame) in that
frame. The counter stops when it is full and self-clears
on read.
Default
--
R/W
RO
SC
Datasheet
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