EP82562ET Datasheet, PDF (12/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

82562ET — Networking Silicon
3.8
Pin Name
ISOL_TEX
TOUT
TESTEN
Pin
Number
Type
29
I
26
O
21
I
Description
Test Execute. The Test Execute signal sets the device into asynchronous
test mode in conjunction with the Test Clock, Test Input, and Test Enable
pins (refer to Table 1, “82562ET Hardware Configuration” on page 3).
In the manufacturing test mode, it places the command that was entered
through the TI pin in the instruction register.
Note: ISOL_TEX has an internal pull-down resistor.
Test Output. The Test Output pin is used for Boundary XOR scan output.
In the manufacturing test mode, it acts as the test output port.
Test Enable. The Test Enable pin is used to enable test mode and should
be externally pulled up to V_CC to enable XOR Tree test mode.
Power and Ground Connections
Pin Name
VCC
VCCP
VCCA
VCCA2
VCCT
VSS
VSSP
VSSA
VSSA2
VCCR
VSSR
Pin
Number
Type
1, 25
36, 40
2,
7,
9, 12,
14, 17
DPS
8, 13, 18 DPS
24, 48
33, 38
3
6
19, 23 APS
20, 22 APS
Description
Digital 3.3 V Power. These pins should be connected to the main digital
power supply.
Digital Ground. These pins should be connected to the main digital
ground.
Analog Power.
Analog Ground. These pins should not be isolated from the main digital.
8
Datasheet