EP82562ET Datasheet, PDF (35/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562ET
6.3.2
Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Table 15. Fast Link Pulse Timing Parameters
Symbol
Parameter
Condition
T8 T_{FLP_WID}
FLP Width (clock
and data)
Clock Pulse to
T9 T_{FLP_CLK_CLK} Clock Pulse
Period
T10
T_{FLP_CLK_DATA}
Clock Pulse to
Data Pulse Period
T11
T_{FLP_BUR_NUM}
Pulses in One
Burst
T12 T_{FLP_BUR_WID} Burst Width
T13 T_{FLP_BUR_PER} FLP Burst Period
Min Typical Max
100
Units
ns
111
125
139
µs
55.5 62.5 69.5
µs
17
33
#
2
ms
8
16
24
ms
Notes
Figure 8. Fast Link Pulse Timings
Fast Link Pulse
FLP Bursts
T10
T8
Clock Pulse
T13
T12
T9
Data Pulse
Clock Pulse
Datasheet
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