EP82562ET Datasheet, PDF (16/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

82562ET — Networking Silicon
4.1.2.2
4.1.2.3
4.2
4.2.1
4.2.1.1
4.2.1.2
Receive Clock and Data Recovery
The clock recovery circuit uses advanced digital signal processing technology to compensate for
various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data
to the MLT-3 decoder.
MLT-3 Decoder, Descrambler, and Receive Digital Section
The 82562ET first decodes the MLT-3 data, and then the descrambler reproduces the 5B symbols
originated in the transmitter. The descrambling is based on synchronization to the transmission of
the 11-bit Linear Feedback Shift Register (LFSR) during an idle phase. The data is decoded at the
4B/5B decoder. After the 4B symbols are obtained, the 82562ET outputs the receive data to the
CSMA unit.
In 100BASE-TX mode, the 82562ET can detect errors in receive data in a number of ways. Any of
the following conditions is considered an error:
• Link integrity fails in the middle of frame reception.
• The start of stream delimiter “JK” symbol is not fully detected after idle.
• An invalid symbol is detected at the 4B/5B decoder.
• Idle is detected in the middle of a frame (before “TR” is detected).
10BASE-T Mode
10BASE-T Transmit Blocks
10BASE-T Manchester Encoder
After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock
performs the Manchester encoding. The Manchester code always has a mid-bit transition. The
boundary transition occurs only when the data is the same from bit to bit. For example, if the value
is 11b, then the change is from low to high within the boundary.
10BASE-T Driver and Filter
Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented
inside the chip. The 82562ET supports both technologies through one pair of transmit differential
pins and by externally sharing the same magnetics.
In 10 Mbps mode the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line
drivers reduce their drive level during the second half of “wide” (100 ns) Manchester pulses and
maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. This
reduces line overcharging during wide pulses, a major source of jitter.
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Datasheet