EP82562ET Datasheet, PDF (28/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

82562ET — Networking Silicon
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
Register 22: Receive Symbol Error Counter Bit Definitions
Bit(s)
Name
15:0 Symbol Error
Counter
Description
This field contains a 16-bit counter that increments for
each symbol error. The counter stops when it is full
and self-clears on read.
In a frame with a bad symbol, each sequential six bad
symbols count as one.
Default
--
R/W
RO
SC
Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter Bit Definitions
Bit(s)
Name
Description
15:0 Premature End of This field contains a 16-bit counter that increments for
Frame
each premature end of frame event. The counter
stops when it is full and self-clears on read.
Default
--
R/W
RO
SC
Register 24: 10BASE-T Receive End of Frame Error Counter Bit
Definitions
Bit(s)
Name
15:0 End of Frame
Counter
Description
This is a 16-bit counter that increments for each end
of frame event. The counter stops when it is full and
self-clears on read.
Default
--
R/W
RO
SC
Register 25: 10BASE-T Transmit Jabber Detect Counter Bit
Definitions
Bit(s)
Name
15:0 Jabber Detect
Counter
Description
This is a 16-bit counter that increments for each
jabber detection event. The counter stops when it is
full and self-clears on read.
Default
--
R/W
RO
SC
Register 27: PHY Unit Special Control Bit Definitions
Bit(s)
Name
15:6 Reserved
5
Switch Probe
Mapping
Description
These bits are reserved and should be set to a
constant 0.
This bit switches the mapping on the LEDs. The LED
mapping is described below in bits 2:0, LED Switch
Control. This bit should always be set to 0b.
Default
0
R/W
RO
0
RW
24
Datasheet