EP82562ET Datasheet, PDF (3/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562ET
Contents
1.0
Introduction......................................................................................................................... 1
1.1 Overview ............................................................................................................... 1
1.2 Features ................................................................................................................ 1
1.3 References ............................................................................................................ 1
1.4 Product Code ........................................................................................................2
2.0
82562ET Architectural Overview........................................................................................ 3
3.0
82562ET Signal Descriptions ............................................................................................. 5
3.1 Signal Type Definitions ......................................................................................... 5
3.2 Twisted Pair Ethernet (TPE) Pins ......................................................................... 5
3.3 External Bias Pins ................................................................................................ 5
3.4 Clock Pins ............................................................................................................ 6
3.5 Platform LAN Connect Interface Pins.................................................................... 6
3.6 LED Pins ..............................................................................................................7
3.7 Miscellaneous Control Pins .................................................................................. 7
3.8 Power and Ground Connections .......................................................................... 8
4.0
Physical Layer Interface Functionality................................................................................ 9
4.1 100BASE-TX Mode ............................................................................................... 9
4.1.1 100BASE-TX Transmit Blocks .................................................................9
4.1.2 100BASE-TX Receive Blocks ................................................................11
4.2 10BASE-T Mode .................................................................................................12
4.2.1 10BASE-T Transmit Blocks ....................................................................12
4.2.2 10BASE-T Receive Blocks .....................................................................13
4.3 Analog References..............................................................................................14
4.4 Dynamic Reduced Power & Auto Plugging Detection.........................................14
4.4.1 Auto Plugging Detection.........................................................................14
4.4.2 Dynamic Reduced Power.......................................................................15
4.4.3 Configuration ..........................................................................................15
4.5 Reset ...................................................................................................................15
4.6 LAN Connect Interface ........................................................................................16
4.6.1 LAN Connect Clock ................................................................................16
4.6.2 LAN Connect Reset................................................................................16
4.7 LED Functionality ...............................................................................................16
5.0
Platform LAN Connect Registers .....................................................................................17
5.1 Medium Dependent Interface Registers 0 through 7...........................................17
5.1.1 Register 0: Control Register Bit Definitions ...........................................17
5.1.2 Register 1: Status Register Bit Definitions ............................................18
5.1.3 Register 2: PHY Identifier Register Bit Definitions ................................19
5.1.4 Register 3: PHY Identifier Register Bit Definitions ................................19
5.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions ....20
5.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions .
20
5.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions ..........20
5.2 Medium Dependent Interface Registers 8 through 15.........................................21
Datasheet
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