EP82562ET Datasheet, PDF (21/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562ET
5.0
5.1
5.1.1
Platform LAN Connect Registers
The following subsections describe PHY registers that are accessible through the LAN Connect
management frame protocol.
Acronyms mentioned in the registers are defined as follows:
SC: Self cleared.
RO: Read only.
RW: Read/Write.
E: EEPROM setting affects content.
LL: Latch low.
LH: Latch high.
Medium Dependent Interface Registers 0 through 7
Register 0: Control Register Bit Definitions
Bit(s)
15
14
13
12
11
Name
Reset
Loopback
Speed Selection
Auto-Negotiation
Enable
Reduced Power
Down
Description
Default R/W
This bit sets the status and control register of the PHY to
their default states and is self-clearing. The PHY returns
a value of one until the reset process has completed and
accepts a read or write transaction.
0 = Normal operation
1 = PHY Reset
0
RW
SC
This bit enables loopback of transmit data nibbles to the
receive data path. The PHY receive circuitry is isolated
from the network.
0
RW
Note that this may cause the descrambler to lose
synchronization and produce 560 nanoseconds of “dead
time.”
Note also that the loopback configuration bit takes priority
over the Loopback MDI bit.
0 = Loopback disabled (normal operation)
1 = 1 = Loopback enabled
This bit is valid on read and controls speed when Auto-
Negotiation is disabled.
0 = 10 Mbps
1 = 100 Mbps
1
RW
This bit enables Auto-Negotiation. Bits 13 and 8, Speed
Selection and Duplex Mode, respectively, are ignored
when Auto-Negotiation is enabled.
0 = Auto-Negotiation disabled
1 = Auto-Negotiation enabled
1
RW
This bit sets the PHY into a low power mode.
0 = Power down disabled (normal operation)
1 = Power down enabled
0
RW
Datasheet
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