EP82562ET Datasheet, PDF (19/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562ET
4.4.2
Dynamic Reduced Power
The 82562ET can be configured to support dynamic reduced power. In the dynamic reduced power
mode, the 82562ET transitions to reduced power mode when an unplugged state is detected. The
82562ET will only return to full power if the reduced power bit on the LAN Connect is reset and a
plugged state is detected. However, if the 82562ET is not configured to support dynamic reduced
power, the 82562ET operates according to the LAN Connect power-down bit (in other words, the
82562ET will operate in reduced power mode only if the LAN Connect power-down bit is set).
4.4.3
Configuration
The dynamic reduced power mode is configured through bit 13 of register 16. The default value is
disabled (0). The status of the 82562ET can be read through bits 10:9 of register 16. When the
82562ET is in reduced power mode, these two bits are set to 1b.
Table 3. Register 16 (10 Hexadecimal): PLC Status, Control and Address Data
Bit
Name
13
Dynamic Reduced Power Down
10
100BASE-TX Power Down
9
10BASE-T Power Down
Description
Read/Write
0 = Automatic reduced power down
enabled
1 = Automatic reduced power down
disabled (default)
Read/Write
The 100BASE-TX Power Down bit indicates
the power state.
0 = Normal operation (default)
1 = Power down
Read Only
The 10BASE-T Power Down bit indicates the
power state.
0 = Normal operation (default)
1 = Power down
Read Only
The 82562ET can enter a reduced power state manually through bit 11 of register 0. This bit is
ORed with the LAN Connect power down bit, which allows the 82562ET to enter a reduced power
state.
Table 4. Register 0: Control Data
Bit
Name
Description
Read/Write
11
Reduced Power Down
0 = Reduced power down disabled (normal
operation; default)
1 = Reduced power down enabled
Read/Write
4.5
Reset
When 82562ET’s Reset signal (RSTSYNC) is asserted for at least 500 µseconds, all internal
circuits are reset. The 82562ET can also be reset through the MII management register reset bit
(register 0, bit 15).
Datasheet
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