HYB25D128160CT Datasheet, PDF (9/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Overview
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Table 1 Ordering Information
Part Number¹⁾
Org. CAS-RCD- Clock
RP
(MHz)
Latencies
CAS-RCD- Clock Speed
RP
(MHz)
Latencies
Package
HYB25D128160CT-5
HYB25D128160CT-6
HYB25D128800CT-6
HYB25D128800CTL-6
HYB25D128400CT-7
HYB25D128400CC-6
×16 3-3-3
200
×16 2.5-3-3 166
×8
×8
×4
×4
2.5 - 3 - 3
2-3-3
166 DDR400B P-TSOPII-66-1
133 DDR333
DDR266A
DDR333 P-FBGA-60-2
HYB25D128160CE–5
×16 3-3-3
200
HYB25D128400CE–6
×4 2.5-3-3 166
HYB25D128800CE–6
×8
HYB25D128800CEL–6 ×8
HYB25D128160CE–6
×16
2.5 - 3 - 3
2-3-3
166 DDR400B P-TSOPII-66-1
133 DDR333
1) HYB: designator for memory components
25D: DDR SDRAMs at V_DDQ = 2.5 V
128: 128-Mbit density
400/800/160: Product variations x4, x8 and x16
C: Die revision C
T/E/C: Package type TSOP and FBGA
L: Low power version (optional) - these components are specifically selected for low I_DD6 Self Refresh currents
-5/6/7/7F/8: speed grade - see Table 1
Data Sheet
9
Rev. 1.0, 2004-04