HYB25D128160CT Datasheet, PDF (59/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Electrical Characteristics
4
Electrical Characteristics
Operating Conditions
Table 12 Absolute Maximum Ratings
Parameter
Symbol
Min.
Voltage on I/O pins relative to V_SS
Voltage on inputs relative to V_SS
Voltage on V_DD supply relative to V_SS
Voltage on V_DDQ supply relative to V_SS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
V_IN, V_OUT
V_IN
V_DD
V_DDQ
T_A
T_STG
P_D
I_OUT
–0.5
–1
–1
–1
0
-55
–
–
Values
Typ. Max.
Unit Note/ Test
Condition
–
V_DDQ +0.5 V –
–
+3.6
V–
–
+3.6
V–
–
+3.6
V–
–
+70
°C –
–
+150
°C –
1.5 –
W–
50 –
mA –
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 13 Input and Output Capacitances
Parameter
Symbol
Input Capacitance: CK, CK
C_I1
Delta Input Capacitance
C_dI1
Input Capacitance:
C_I2
All other input-only pins
Delta Input Capacitance:
All other input-only pins
C_dIO
Input/Output Capacitance: DQ, DQS, DM C_IO
Min.
1.5
2.0
—
1.5
2.0
—
3.5
4.0
Values
Unit
Typ. Max.
—
2.5
pF
—
3.0
pF
—
0.25 pF
—
2.5
pF
—
3.0
pF
—
0.5
pF
—
4.5
pF
—
5.0
pF
Note/
Test Condition
P-TFBGA-60-2 ¹⁾
P-TSOPII-66-1 ¹⁾
1)
P-TFBGA-60-2 ¹⁾
P-TSOPII-66-1 ¹⁾
1)
P-TFBGA-60-2 ¹⁾²⁾
P-TSOPII-66-1
1)2)
Delta Input/Output Capacitance:
DQ, DQS, DM
C_dIO
—
—
0.5
pF
1)
1) These values are guaranteed by design and are tested on a sample base only. V_DDQ = V_DD = 2.5 V ± 0.2 V, f = 100 MHz,
T_A = 25 °C, V_OUT(DC) = V_DDQ/2, V_OUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace
matching at the board level.
Data Sheet
59
Rev. 1.0, 2004-04