HYB25D128160CT Datasheet, PDF (68/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 19 AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100
Parameter
Symbol –5
–6
–7
Unit
DDR400B
DDR333
DDR266A
Min. Max. Min. Max. Min. Max.
Active to Autoprecharge delay t_RAP
Active bank A to Active bank B t_RRD
command
t_RCD or
t_RASmin
10 —
t_RCD or
t_RASmin
12 —
t_RCD or t_RASmin ns
15
—
ns
Write recovery time
t_WR
15 —
15 —
15
ns
Auto precharge write recovery + t_DAL
precharge time
(t_WR/t_CK) + (t_RP/t_CK)
t_CK
Internal write to read command t_WTR 2
—
1
—
1
delay
—
t_CK
Exit self-refresh to non-read
command
t_XSNR 75
—
75 —
75 —
ns
Exit self-refresh to read
command
t_XSRD 200 —
200 —
200 —
t_CK
Average Periodic Refresh
Interval
t_REFI — 15.6 — 15.6 —
15.6 µs
Note/ Test
Condition
1)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between V_IH(ac) and V_IL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
68
Rev. 1.0, 2004-04