HYB25D128160CT Datasheet, PDF (18/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

Rev. 1.0, 2004-04
18
Data Sheet
Figure 4 Block Diagram 128Mbit ×32 Mbit ×8
Row-Address MUX
Refresh Counter
Address Register
Bank Control Logic
Bank0
Row-Address Latch
& Decoder
Drivers
Read Latch
Receivers
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration