HYB25D128160CT Datasheet, PDF (34/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
Data from any Read burst may be truncated with a Burst Terminate command, as shown on Figure 14. The Burst
Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles
after the Read command, where x equals the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must be used, as shown on Figure 15. The example is
shown for t_DQSS(min). The t_DQSS(max) case, not shown here, has a longer bus idle time. t_DQSS(min) and t_DQSS(max) are
defined in Chapter 3.5.3.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto
Precharge was not activated). The Precharge command should be issued x cycles after the Read command,
where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This
is shown on Figure 16 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent
command to the same bank cannot be issued until t_RP is met. Note that part of the row precharge time is hidden
during the access of the last data elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same Read burst with Auto Precharge
enabled. The disadvantage of the Precharge command is that it requires that the command and address busses
be available at the appropriate time to issue the command. The advantage of the Precharge command is that it
can be used to truncate bursts.
Data Sheet
34
Rev. 1.0, 2004-04