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HYB25D128160CT Datasheet, PDF (32/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2
Read
BAa, COL n
NOP
CL=2
NOP
Read
BAa, COL b
NOP
DO a-n
NOP
DOa- b
CK
CK
Command
Address
Read
BAa, COL n
DQS
DQ
NOP
NOP
CL=2.5
Read
BAa, COL b
DO a-n
CAS Latency = 2.5
NOP
NOP
NOP
DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).
Shown with nominal tAC, tDQSCK, and tDQSQ.
Don’t Care
Figure 12 Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
Data Sheet
32
Rev. 1.0, 2004-04