HYB25D128160CT Datasheet, PDF (14/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
Table 2 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
14, 17, 19, 25, NC
43, 50
NC
—
Not Connected
×16,×8 and ×4 organization
Table 3
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected (JEDEC Standard)
Table 4
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Data Sheet
14
Rev. 1.0, 2004-04