HYB25D128160CT Datasheet, PDF (35/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2
Read
BAa, COL n
NOP
CL=2
BST
NOP
NOP
NOP
DOa-n
No further output data after this point.
DQS tristated.
CAS Latency = 2.5
Read
BAa, COL n
NOP
BST
NOP
NOP
NOP
CL=2.5
DOa-n
No further output data after this point.
DQS tristated.
DO a-n = data out from bank a, column n.
Cases shown are bursts of 8 terminated after 4 data elements.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 14 Terminating a Read Burst: CAS Latencies (Burst Length = 8)
Don’t Care
Data Sheet
35
Rev. 1.0, 2004-04