HYB25D128160CT Datasheet, PDF (71/85 Pages) Infineon Technologies AG – 128 Mbit Double Data Rate SDRAM

HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Electrical Characteristics
4.3.1
I_DD Current Measurement Conditions
Legend: A = Activate, R = Read, RA = Read with Autoprecharge, P = Precharge, N = NOP or DESELECT
I_DD1: Operating Current: One Bank Operation
1. General test condition
a) Only one bank is accessed with t_RC,MIN.
b) Burst Mode, Address and Control inputs are changing once per NOP and DESELECT cycle.
c) 50% of data changing at every transfer
d) I_OUT = 0 mA.
2. Timing patterns
a) DDR266A (133 MHz, CL = 2): t_CK = 7.5 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 9 × t_CK, t_RAS = 5 × t_CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing
b) DDR333B (166 MHz, CL = 2.5): t_CK = 6 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 9 × t_CK, t_RAS = 5 × t_CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing
c) DDR400B (200 MHz, CL = 3): t_CK = 5 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 11 × t_CK, t_RAS = 8 × t_CK
Setup:A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing
I_DD7: Operating Current: Four Bank Operation
1. General test condition
a) Four banks are being interleaved with t_RCMIN.
b) Burst Mode, Address and Control inputs on NOP edge are not changing.
c) 50% of data changing at every transfer
d) I_OUT = 0 mA.
2. Timing patterns
a) DDR266A (133 MHz, CL = 2): t_CK = 7.5 ns, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 × t_CK, t_RAS = 5 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
b) DDR333B (166 MHz, CL = 2.5): t_CK = 6 ns, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 × t_CK, t_RAS = 5 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
c) DDR400B (200 MHz, CL = 3): t_CK = 5 ns, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 *× t_CK, t_RAS = 8 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address
Data Sheet
71
Rev. 1.0, 2004-04