TC1762 Datasheet, PDF (64/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1762
Preliminary
Functional Description
3.21
Clock Generation and PLL
The TC1762 clock system performs the following functions:
• Acquires and buffers incoming clock signals to create a master clock frequency
• Distributes in-phase synchronized clock signals throughout the TC1762’s entire clock
tree
• Divides a system master clock frequency into lower frequencies required by the
different modules for operation.
• Dynamically reduces power consumption during operation of functional units
• Statically reduces power consumption through programmable power-saving modes
• Reduces electromagnetic interference (EMI) by switching off unused modules
The clock system must be operational before the TC1762 can function, so it contains
special logic to handle power-up and reset operations. Its services are fundamental to
the operation of the entire system, so it contains special fail-safe logic.
Features
• PLL operation for multiplying clock source by different factors
• Direct drive capability for direct clocking
• Comfortable state machine for secure switching between basic PLL, direct or
prescaler operation
• Sleep and Power-Down Mode support
The TC1762 Clock Generation Unit (CGU) as shown in Figure 3-14 allows a very
flexible clock generation. It basically consists of an main oscillator circuit and a Phase-
Locked Loop (PLL). The PLL can converts a low-frequency external clock signal from the
oscillator circuit to a high-speed internal clock for maximum performance.
The system clock f_SYS is generated from an oscillator clock f_OSC in either one of the four
hardware/software selectable ways:
• Direct Drive Mode (PLL Bypass):
In Direct Drive Mode, the TC1762 clock system is directly driven by an external clock
signal. input, i.e. f_CPU = f_OSC and f_SYS = f_OSC. This allows operation of the TC1762 with
a reasonably small fundamental mode crystal.
• VCO Bypass Mode (Prescaler Mode):
In VCO Bypass Mode, f_CPU and f_SYS are derived from f_OSC by the two divider stages,
P-Divider and K-Divider. The system clock f_SYS is equal to f_CPU.
• PLL Mode:
In PLL Mode, the PLL is running. The VCO clock f_VCO is derived from f_OSC, divided by
the P factor, multiplied by the PLL (N-Divider). The clock signals f_CPU and f_SYS are
derived from f_VCO by the K-Divider. The system clock f_SYS is equal to f_CPU.
• PLL Base Mode:
In PLL Base Mode, the PLL is running at its VCO base frequency and f_CPU and f_SYS
Data Sheet
60
V1.0, 2008-04