TC1762 Datasheet, PDF (33/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1762
Preliminary
Functional Description
3.5
DMA Controller and Memory Checker
The DMA Controller of the TC1762 transfers data from data source locations to data
destination locations without intervention of the CPU or other on-chip devices. One data
move operation is controlled by one DMA channel. Eight DMA channels are provided in
one DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Block to
the two FPI Bus interfaces and an MLI bus interface. In the TC1762, the FPI Bus
interfaces are connected to the System Peripheral Bus and the DMA Bus. The third
specific bus interface provides a connection to the Micro Link Interface module (MLI0 in
the TC1762) and other DMA-related devices (Memory Checker module in the TC1762).
Clock control, address decoding, DMA request wiring, and DMA interrupt service request
control are implementation-specific and managed outside the DMA controller kernel.
Figure 3-1 shows the implementation details and interconnections of the DMA module.
Clo ck
f_DMA
Co n tr o l
DMA Controller
DMA
Re q u e sts
of
On-chip
Periph.
Un its
DMA Sub-Block 0
Request
CSHe0lne _ctOioUnT/
A rb itra tio n
DMA
Channels
00-07
Transaction
Control Unit
Bus
S witch
A d d r e ss
Decoder
Interrupt _SR[15:0]
Request
Nodes
DMA Interrupt Control
A rb ite r/
S witch
Control
Figure 3-1 DMA Controller Block Diagram
Features
• 8 independent DMA channels
Data Sheet
29
S yste m
Periphera
Bus
DMA Bus
MLI0
Memory
Ch e cke r
MCB06149
V1.0, 2008-04