TC1762 Datasheet, PDF (39/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1762
Preliminary
Functional Description
3.8
High-Speed Synchronous Serial Interface (SSC0)
Figure 3-4 shows a global view of the functional blocks and interfaces of the high-speed
Synchronous Serial Interface, SSC0.
Clock
Control
f_{SSC 0}
f_{C L C0}
Address
Decoder
EIR
Interrupt TIR
Control RIR
To
DMA
SSC0_RDR
SSC0_TDR
M/S Select ¹⁾
Enable ¹⁾
SSC0
Module
(Kernel )
Master
MRSTA
MRSTB
MTSR
Slave
MTSRA
MTSRB
MRST
Slave
Master
Slave
SCLKA
SCLKB
SCLK
SLSI1
SLSI[7:2] ¹⁾
SLSO[2:0]
Port 3
Control
Master
SLSO[5:3]
SLSO6
SLSO7 ¹⁾
A2 P3.4 /MTSR0
A2 P3.3 /MRST0
A2 P3.2 /SCLK0
A2 P3.7 /SLSI0
A2 P3.5 /SLSO00
A2 P3.6 /SLSO01
A2 P3.7 /SLSO02
A2 P3.8 /SLSO06
Port 2
Control
A2 P2.1 /SLSO03
A2 P2.8 /SLSO04
A2 _{P2.9 /SLSO05}
1) These lines are not connected
MCB06225
Figure 3-4 Block Diagram of the SSC Interfaces
The SSC supports full-duplex and half-duplex serial synchronous communication up to
40.0 MBaud at 80 MHz module clock and up to 33 MBaud at 66 MHz module clock. The
serial clock signal can be generated by the SSC itself (Master Mode) or can be received
from an external master (Slave Mode). Data width, shift direction, clock polarity and
phase are programmable. This allows communication with SPI-compatible devices.
Transmission and reception of data is double-buffered. A shift clock generator provides
the SSC with a separate serial clock signal. Seven slave select inputs are available for
Data Sheet
35
V1.0, 2008-04