TC1762 Datasheet, PDF (106/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1762
Preliminary
Electrical Parameters
4.3.8 Peripheral Timings
Section 4.3.8 provides the characteristics of the peripheral timings in the TC1762.
Note: Peripheral timing parameters are not subject to production test. They are verified
by design/characterization.
4.3.8.1 Micro Link Interface (MLI) Timing
Table 4-17 provides the characteristics of the MLI timing in the TC1762.
Table 4-17 MLI Timing (Operating Conditions apply, C_L = 50 pF)
Parameter
Symbol
Limit Values
TCLK clock period¹⁾²⁾
RCLK clock period
MLI outputs delay from TCLK
Min.
Max.
t₃₀
CC 2³⁾
–
t₃₁
SR 1
–
t₃₅
CC 0
8
MLI inputs setup to RCLK
t₃₆
SR 4
–
MLI inputs hold to RCLK
t₃₇
SR 4
–
RREADY output delay from RCLK
t₃₈
CC 0
8
1) TCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) TCLK high and low times can be minimum 1 × T_MLI
3) T_MLImin = T_SYS = 1/f_SYS. When f_SYS = 80MHz, t₃₀ = 25ns
Unit
1/f_SYS
1/f_SYS
ns
ns
ns
ns
Data Sheet
102
V1.0, 2008-04