TC1762 Datasheet, PDF (28/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1762
Preliminary
Functional Description
3
Functional Description
Chapter 3 provides an overview of the TC1762 functional description.
3.1
System Architecture and On-Chip Bus Systems
The TC1762 has two independent on-chip buses (see also TC1762 block diagram on
Page 2-6):
• Local Memory Bus (LMB)
• System Peripheral Bus (SPB)
The LMB Bus connects the CPU local resources for data and instruction fetch. The Local
Memory Bus interconnects the memory units and functional units, such as CPU and
PMU. The main target of the LMB bus is to support devices with fast response times,
optimized for speed. This allows the DMI and PMI fast access to local memory and
reduces load on the FPI bus. The Tricore system itself is located on LMB bus.
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. It supports 8-, 16-, 32- and 64-bit single transactions and variable
length 64-bit block transfers.
The SPB Bus is accessible to the CPU via the LMB Bus bridge. The System Peripheral
Bus (SPB Bus) in TC1762 is an on-chip FPI Bus. The FPI Bus interconnects the
functional units of the TC1762, such as the DMA and on-chip peripheral components.
The FPI Bus is designed to be quick to be acquired by on-chip functional units, and quick
to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast
FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is
designed to sustain high transfer rates. For example, a peak transfer rate of up to 320
Mbyte/s can be achieved with a 80 MHz bus clock and 32-bit data bus. With a 66 MHz
bus clock, the peak transfer rate is up to 264 Mbytes/s. Multiple data transfers per bus
arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth.
Both the LMB Bus and the SPB Bus runs at full CPU speed. The maximum CPU speed
is 66 or 80 MHz depending on the derivative.
Additionally, two simplified bus interfaces are connected to and controlled by the DMA
Controller:
• DMA Bus
• SMIF Interface
Data Sheet
24
V1.0, 2008-04