TC1762 Datasheet, PDF (35/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1762
Preliminary
Functional Description
3.6
Interrupt System
The TC1762 interrupt system provides a flexible and time-efficient means of processing
interrupts. An interrupt request is serviced by the CPU, which is called the “Service
Provider”. Interrupt requests are called “Service Requests” rather than “Interrupt
Requests” in this document.
Each peripheral in the TC1762 can generate service requests. Additionally, the Bus
Control Units, the Debug Unit, and even the CPU itself can generate service requests to
the Service Provider.
As shown in Figure 3-2, each TC1762 unit that can generate service requests is
connected to one or multiple Service Request Nodes (SRN). Each SRN contains a
Service Request Control Register mod_SRCx, where “mod” is the identifier of the
service requesting unit and “x” an optional index. The CPU Interrupt Arbitration Bus
connects the SRNs with the Interrupt Control Unit (ICU), which arbitrates service
requests for the CPU and administers the CPU Interrupt Arbitration Bus.
The Debug Unit can generate service requests to the CPU. The CPU makes service
requests directly to itself (via the ICU). The CPU Service Request Nodes are activated
through software.
Depending on the selected system clock frequency f_SYS, the number of f_SYS clock cycles
per arbitration cycle must be selected as follows:
• f_SYS < 60 MHz: ICR.CONECYC = 1
• f_SYS > 60 MHz: ICR.CONECYC = 0
Data Sheet
31
V1.0, 2008-04