TC1762 Datasheet, PDF (54/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1762
Preliminary
Functional Description
Clock
Control
f_FADC
f_CLC
Address
Decoder
Interrupt ^SR[1:0]
Control
DMA
SR[3:2]
V_FAREF V_DDAF V_DDMF
V_FAGND V_SSAF
V_SSMF
FADC
Module
Kernel
FAIN0P
FAIN0N
FAIN1P
FAIN1N
D AN32
D AN33
D AN34
D AN35
GPTA0
OUT1
OUT9
OUT18
OUT26
OUT2
OUT10
OUT19
OUT27
GS[7:0]
TS[7:0]
PDOUT2
External Request Unit
(SCU)
PDOUT3
Figure 3-11 Block Diagram of the FADC Module
A1 P3.10 / REQ0
A1 P3.11 / REQ1
A1 P0.14 / REQ4
A1 P0.15 / REQ5
MCA06445
Features
• Extreme fast conversion, 21 cycles of f_FADC clock (262.5 ns @ f_FADC = 80 MHz and
318.2 ns @ f_FADC = 66 MHz)
• 10-bit A/D conversion
– Higher resolution by averaging of consecutive conversions is supported
• Successive approximation conversion method
• Two differential input channels
• Offset and gain calibration support for each channel
• Differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel
• Free-running (Channel Timers) or triggered conversion modes
• Trigger and gating control for external signals
• Built-in Channel Timers for internal triggering
• Channel timer request periods independently selectable for each channel
Data Sheet
50
V1.0, 2008-04