TC1762 Datasheet, PDF (101/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

Preliminary
TC1762
Electrical Parameters
±1.40
±1.30
±1.20
TC1762 PLL Jitter (preliminary )
f_CPU = 40 MHz
f _{CP U} = 66 MHz
±1 .1 0
±1 .0 0
f_CPU = 80 MHz
±0 .9 0
1
2
3
4
5
P [Periods]
Figure 4-13 Approximated Maximum Accumulated PLL Jitter for Typical CPU
Clock Frequencies f_CPU (detail)
Note: The maximum peak-to-peak noise on the main oscillator and PLL power supply
(measured between V_DDOSC and V_SSOSC) is limited to a peak-to-peak voltage of
V_PP = 10 mV. This condition can be achieved by appropriate blocking to the supply
pins and using PCB supply and ground planes.
Data Sheet
97
V1.0, 2008-04