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TC1762 Datasheet, PDF (38/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore | |||
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TC1762
Preliminary
Functional Description
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal, which can be accurately adjusted
by a prescaler implemented as fractional divider.
Features
⢠Full-duplex asynchronous operating modes
â 8-bit or 9-bit data frames, LSB first
â Parity-bit generation/checking
â One or two stop bits
â Baud rate from 5.0 Mbit/s to 1.19 bit/s (@ 80 MHz module clock) and 4.1Mbit/s to
0.98 bit/s (@ 66 MHz module clock)
â Multiprocessor mode for automatic address/data byte detection
â Loop-back capability
⢠Half-duplex 8-bit synchronous operating mode
â Baud rate from 10.0 Mbit/s to 813.8 bit/s (@ 80 MHz module clock) and 8.25 Mbit/s
to 671.4 bit/s (@ 66 MHz module clock)
⢠Double-buffered transmitter/receiver
⢠Interrupt generation
â On a transmit buffer empty condition
â On a transmit last bit of a frame condition
â On a receive buffer full condition
â On an error condition (frame, parity, overrun error)
Data Sheet
34
V1.0, 2008-04
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