TC1762 Datasheet, PDF (58/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1762
Preliminary
Functional Description
3.16
Watchdog Timer
The WDT provides a highly reliable and secure way to detect and recover from software
or hardware failure. The WDT helps to abort an accidental malfunction of the TC1762 in
a user-specified time period. When enabled, the WDT will cause the TC1762 system to
be reset if the WDT is not serviced within a user-programmable time period. The CPU
must service the WDT within this time interval to prevent the WDT from causing a
TC1762 system reset. Hence, routine service of the WDT confirms that the system is
functioning as expected.
In addition to this standard “Watchdog” function, the WDT incorporates the End-of-
Initialization (Endinit) feature and monitors its modifications. A system-wide line is
connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection). Registers protected via this line
can only be modified when Supervisor Mode is active and bit ENDINIT = 0.
A further enhancement in the TC1762’s WDT is its reset prewarning operation. Instead
of resetting the device upon the detection of an error immediately (the way that standard
Watchdogs do), the WDT first issues a Non-Maskable Interrupt (NMI) to the CPU before
resetting the device at a specified time period later. This step gives the CPU a chance to
save the system state to the memory for later investigation of the cause of the
malfunction; an important aid in debugging.
Features
• 16-bit Watchdog counter
• Selectable input frequency: f_SYS/256 or f_SYS/16384
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated Password Access mechanism with fixed and user-definable password
fields
• Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and is limited.
• Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
• Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
• Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system
malfunction is assumed and the TC1762 is held in reset until a power-on or hardware
reset occurs. This prevents the device from being periodically reset if, for instance,
connection to the external memory has been lost such that system initialization could
not even be performed.
Data Sheet
54
V1.0, 2008-04