STAC9758 Datasheet, PDF (94/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
Bit(s) R/W Reset Value Name
Description
9:5 RW see table
DL4:DL0
Buffer delays: CODEC will provide a delay measurement for the input and
output channels. Software will use this value to accurately calculate audio
stream position with respect to what is been reproduced or recorded. These
values are in 20.83 microsecond (1/48000 second) units.
For output channels, this timing is from the end of AC-Link frame in which the
sample is provided, until the time the analog signal appears at the output pin.
For input streams, this is from when the analog signal is presented at the pin
until the representative sample is provided on the AC-Link.
The measurement is a typical measurement, at a 48KHz sample rate,
with minimal in-CODEC processing (i.e., 3D effects are turned off.)
00h - Information not provided
01h…1Eh - Buffer delay in 20.83 µsec units
1Fh - reserved
These bits are read/write and do not reset on RESET#.
The default value is the delay internal to the CODEC. The BIOS may add to this
value the known delays external to the CODEC, such as for an external
amplifier.
4 RW see table
Information Valid Bit: Indicates whether a sensing method is provided by the
CODEC and if information field is valid. This field is updated by the CODEC.
0h--After CODEC RESET# de-assertion, it indicates the CODEC does NOT
provides sensing logic and this bit will be Read Only. After a sense cycle is
completed indicates that no information is provided on the sensing method.
1h--After CODEC RESET# de-assertion, it indicates the CODEC provides
IV
sensing logic for this I/O and this bit is Read/Write. After clearing this bit
by writing 1, when a sense cycle is completed the assertion of this bit
indicates that there is valid information in the remaining descriptor bits.
Writing 0 to this bit has no effect.
BIOS should NOT write this bit, as it is reset on RESET#.
See Table 22: page96 for details on usage of this bit.
3:1 0
0
RESERVED Bit not used, should read back 0
0 RO see table
Function Information Present
FIP
This bit set to 1 indicates that the G[4:0], INV, DL[4:0] (Register 6Ah) are
supported and R/W capable.
This bit is Read Only.
G[4:0]
00000
00001
01111
10001
11111
Table 21. Gain or Attenuation Examples
Gain or Attenuation (dB relative to level-out)
0 dBV
1.5 dBV
24 dBV
-1.5 dBV
-24 dBV
IDT™
94
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206