STAC9758 Datasheet, PDF (36/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least
significant bits.
When mono audio sample streams are output from the AC‘97 Controller, it is necessary that BOTH
left and right sample stream time slots be filled with the same data.
5.3.1. Slot 0: TAG / CODEC ID
Table 7. Output Slot 0 Bit Definitions
Bit
Description
15
Frame Valid
14
Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only)
13
Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only)
Slot 3-12 - Slot-Valid-Data bits
12
Slot 3: PCM Left channel
11
Slot 4: PCM Right channel
10
Slot 5: Modem Line 1 (not used on STAC9758/9759)
9
Slot 6: Alternative PCM1 Left
8
Slot 7: Alternative PCM2 Left
7
Slot 8: Alternative PCM2 Right
6
Slot 9: Alternative PCM1 Right
5
Slot 10: SPDIF Left
4
Slot 11: SPDIF Right
3
Slot 12: Audio GPIO
2
Reserved (Set to 0)
1-0 2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)
Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains
at least one time slot of valid data. The next 12 bit positions sampled by AC‘97 indicate which of the
corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can
be transmitted across AC-Link at its fixed 48 KHz audio frame rate.
The two LSBs of Slot 0 transmit the CODEC ID used to distinguish Primary and Secondary CODEC
register access.
5.3.2.
Slot 1: Command Address Port
The command port is used to control features, and monitor status (see AC-Link input frame Slots 1
and 2) for AC‘97 CODEC functions including, but not limited to, mixer settings, and power manage-
ment (refer to the control register section of this specification).
The control interface architecture supports up to 64 16-bit read/write registers, addressable on even
byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h,
03h, etc.) accesses are reserved for future expansion.
IDT™
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HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206