STAC9758 Datasheet, PDF (75/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
Bit(s) Reset Value R/W
Name
Description
SPDIF slot assignment
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
5:4
11
RW
SPSA1:SPSA0
The DRS (Double Rate SPDIF) bit causes the primary data to be taken
from slots 3&4. The secondary data is taken from the slots indicated by
SPSA.
If SPSA bits are set to 00 (slot pair 3/4) and DRS bit (Double Rate
SPDIF) is set to 1, then the 20-bit data to DAC-A will be doubled. This
will not sound particularly bad, but is an operating mode which provides
little benefit.
3
0
RO RESERVED Reserved
0 = Disables SPDIF (SPDIF_OUT is high Z )
2
0
RW
SPDIF
1 = Enable SPDIF
SPDIF is a control bits for Reg 3Ah. This bit must be set low, i.e. SPDIF
disabled, in order to write to Reg 3Ah Bits D15,D13:D0.
Double Rate Audio
0 = Disabled
1 = Enabled
When DRA bit is set, then the DSA bits (Reg 28, Bits D5:D4) have no
effect.
Data from PCM L and PCM R in output slots 3 and 4 is used in
1
0
RW
DRA
conjunction with PCM L (n+1) and PCM R (n+1) data , to provide DAC
streams at twice the sample rate designated by the PCM Front Sample
Rate Control Register. The slots on which the (n+1) data is transmitted
on is indicated by the DRSS[1:0] bits in the General Purpose Register
20h.
Note that DRA can be used without VRA, in that case the converter
rates are forced to 96 KHz if DRA = 0.
Variable Rate Audio Enable
0 = Disabled
DAC and ADC set to 48 KHz
0
0
RW VRA Enable Reg 2Ch, Reg 2Eh, Reg 30h & Reg 32h all read back BB80h
1 = Enabled
Reg 2Ch, Reg 2Eh, Reg 30h & Reg 32h control the various DAC and
ADCsample rates
8.2.21.1. Variable Rate Audio Enable
The Extended Audio Status Control register also contains one active bit to enable or disable the
Variable Sampling Rate capabilities of the DACs and ADCs. If VRA Enable ( Reg 20h, bit D0) is 1,
the variable sample rate control registers (2Ch, 2Eh, 30h, and 32h) are active, and “on-demand” slot
data required transfers are allowed. If the VRA bit is 0, the DACs and ADCs will operate at the
default 48 KHz data rate.
The STAC9758/9759 supports “on-demand” slot request flags. These flags are passed from the
CODEC to the AC’97 controller in every audio input frame. Each time a slot request flag is set (active
low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot
in the audio frame that immediately follows. The VRA Enable bit must be set to 1 to enable
“on-demand” data transfers. If the VRA Enable bit is not set, the CODEC will default to 48KHz trans-
IDT™
75
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206