STAC9758 Datasheet, PDF (86/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
Reg
NAME
6Ch DAC Slot Mapping
6Eh ADC Slot Mapping
FUNCTION
Allows the controlling software to modify the default slot to the
DAC mappings.
Allows the controlling software to modify the default slot to the
ADC mappings.
Location
8.6.14: page97
8.6.16: page100
8.6.1. SPDIF_In Status 1 Register (60h, Page 00h)
Register 24h must be set to Page 00h to access this register.
Default:0000h
D15
D14
D13
D12
D11
D10
LVL
CC6
CC5
CC4
CC3
CC2
D7
D6
D5
D4
D3
D2
MODE1
MODE0
PRE2
PRE1
PRE0
CPY
D9
CC1
D1
/AUD
D8
CC0
D0
PRO
First of 2 registers that echo the status bits taken from the SPDIF input stream header. All bits relate
directly to the defined header bits for IEC60958. No translation or inversion necessary.
Bit(s) Reset Value R/W Name
Description
15
0
RO LVL Generation level
Category Code
14:8
0
RO CC<6:0> IEC spec “ The category code indicates the kind of equipment that
generates the digital audio interface signal.”
7:6
0
RO Mode<1:0> Mode
5:3
0
RO PRE<2:0> Pre emphesis
2
0
RO CPY COPY
Non PCM / PCM
1
0
RO /AUD 0 = PCM data
1 = non PCM (AC3). If SPDIF is routed to DAC-B, this will mute DAC-B.
Professional / consumer
0
0
RO PRO 0 = consumer
1 = professional
8.6.2. CODEC Class/Rev (60h Page 01h)
Register 24h must be set to Page 01h to access this register.
Default: 18xxh
D15
D14
D13
D12
D11
D10
D9
D8
RESERVED
CL4
CL3
CL2
CL1
CL0
D7
D6
D5
D4
D3
D2
D1
D0
RV7
RV6
RV5
RV4
RV3
RV2
RV1
RV0
IDT™
86
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206