STAC9758 Datasheet, PDF (68/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
8.2.18. Audio Interrupt and Paging (24h)
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
I4
I3
I2
I1
I0
RESERVED
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
PG3
PG2
PG1
PG0
Bit(s) Reset Value R/W
15
0
RW
14-13
0
RO
12
0
RW
11
0
RW
Name
I4
I3-I2
I1
I0
Description
0 = Interrupt is clear
1 = interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt enable (I0)
status. An interrupt in the GPI in slot 12 in the ACLink will follow this bit
change when interrupt enable (I0) is unmasked.
Interrupt Cause
00 = Reserved
01 = Sense Cycle Complete, sense info available.
10 = Change in GPIO input status
11 = Sense Cycle Complete and Change in GPIO input status.
These bits will reflect the general cause of the first interrupt event
generated. It should be read after interrupt status has been confirmed as
interrupting. The information should be used to scan possible interrupting
events in proper pages.
Sense Cycle
0 = Sense Cycle not in Progress
1 = Sense Cycle Start.
Writing a 1 to this bit causes a sense cycle start if supported. If sense cycle
is not supported this bit is read only.
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver should not un-mask the interrupt unless ensured by the AC‘97
Controller that no conflict is possible with modem slot 12 - GPI
functionality. Some AC’97 2.2 compliant controllers may not support audio
CODEC interrupt infrastructure. In either case, software should poll the
interrupt status after initiating a sense cycle and wait for Sense Cycle Max
Delay to determine if an interrupting event has occurred.
IDT™
68
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206