STAC9758 Datasheet, PDF (35/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
5.3.
AC-Link Output Frame (SDATA_OUT)
The AC-Link output frame data streams correspond to the multiplexed bundles of all digital output
data targeting AC‘97’s DAC inputs, and control registers. As mentioned earlier, each AC-Link output
frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot contain-
ing 16-bits which are used for AC-Link protocol infrastructure.
Figure 14 illustrates the time slot based AC-Link protocol.
Figure 14. AC-Link Audio Output Frame
Tag Phase
Data Phase
20.8 uS (48 kHZ)
SYNC
BIT_CLK
12.288 MHz
SDATA_OUT
valid
Frame
slot1 slot2
slot(12) _{"0" CID1 CID0 1 9}
"0" 19
"0" 1 9
"0"
19
"0"
End of previous audio frame
Time Slot "Valid" Bits
("1" = time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
A new AC-Link output frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97
CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Con-
troller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posi-
tion is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97
CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure 15. Start of an Audio Output Frame
SYNC
asserted
first
SDATA_OUT
bit of frame
SYNC
BIT_CLK
SDATA_OUT
valid
Frame
slot1 slot2
End of previous audio frame
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions
stuffed with 0 by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and valid
time slot, the AC‘97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0.
As an example, consider an 8-bit sample stream that is being played out to one of the STAC9758/
9759 DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next
12 bit-positions which are stuffed with 0 by the AC‘97 Controller. This ensures that regardless of the
IDT™
35
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206