STAC9758 Datasheet, PDF (29/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
4.6. AC-Link Power Management
4.6.1.
Powering down the AC-Link
The AC-Link signals can be placed in a low power mode. When AC‘97’s Powerdown Register (26h)
is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a
logic low voltage level. After signaling a reset to AC‘97, the AC‘97 Controller should not attempt to
play or capture audio data until it has sampled a CODEC Ready indication from AC‘97.
SYNC
BIT_CLK
SDATA_OUT
slot 2
per
frame
TAG
Write to
0x20
DATA
PR4
SDATA_IN
slot 2
per
frame
TAG
Note: BIT_CLK not to scale
Figure 12. STAC9758/9759 Powerdown Timing
BIT_CLK and SDATA_IN are transitioned low immediately following decode of the write to the Pow-
erdown Register (26h) with PR4. When the AC‘97 Controller driver is at the point where it is ready to
program the AC-Link into its low power mode, slots 1 and 2 are assumed to be the only valid stream
in the audio output frame.
After programming the AC‘97 device to this low power, halted mode, the AC‘97 Controller is required
to drive and keep SYNC and SDATA_OUT low.
Once the AC‘97 CODEC has been instructed to halt BIT_CLK, a special “wake-up” protocol must be
used to bring the AC-Link to the active mode since normal audio output and input frames can not be
communicated in the absence of BIT_CLK.
4.6.2.
Waking up the AC-Link
There are two methods for bringing the AC-Link out of a low power, halted mode. Regardless of the
method, it is the AC‘97 Controller that performs the wake-up task.
4.6.2.1. Controller Initiates Wake-up
AC-Link protocol provides for a “Cold AC‘97 Reset”, and a “Warm AC‘97 Reset”. The current power
down state would ultimately dictate which form of AC‘97 reset is appropriate. Unless a “cold” or “reg-
ister” reset (a write to the Reset Register) is performed (wherein the AC‘97 registers are initialized to
their default values), registers are required to keep state during all power down modes.
Once powered down, re-activation of the AC-Link via re-assertion of the SYNC signal must not occur
for a minimum of four audio frame times following the frame in which the power down was triggered.
When AC-Link powers up, the CODEC indicates readiness via the CODEC Ready bit (input slot 0,
bit 15).
IDT™
29
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206