STAC9758 Datasheet, PDF (40/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
5.4.1.2. Status Address Port
The status port is used to monitor status for the STAC9758/9759 functions including, but not limited
to, mixer settings and power management. AC-Link input frame slot 1s stream echoes the control
register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1
and 2 had been tagged “valid” by the AC‘97 CODEC during slot 0.)
Bit
19
18:12
11:2
1:0
Table 10. Status Address Port Bit Assignments
Description
Reserved
Control Register Index
SLOTREQ
Reserved
Comments
Stuffed with 0
Echo of register index for which data is being returned
See Next Section
Stuffed with 0
The first bit (MSB) generated by AC‘97 is always stuffed with a 0. The following 7 bit positions com-
municate the associated control register address, the next 10 bits support AC‘97’s variable sample
rate signaling protocol, and the trailing 2 bit positions are stuffed with 00 by AC‘97.
5.4.1.3. SLOTREQ Signaling Bits
AC-Link input frame Slot #1, the Status Address Port, now delivers CODEC control register read
address and variable sample rate slot request flags for all output slots. Ten of the formerly reserved
least significant bits have been defined as data request flags for output slots 3-12.
The AC-Link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY
indicates valid Status Address Port data (Control Register Index). The CODEC should only set
SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to 1 when returning valid data from a previ-
ous register read. They should otherwise be set to 0. SLOTREQ bits have validity independent of the
Slot 1 tag bit.
SLOTREQ bits are always 0 in the following cases
• Fixed rate mode (VRA = 0)
• Inactive (powered down) DAC channel
SLOTREQ bits are only set to 1 by the CODEC in the following case
• Variable rate audio mode (VRA = 1) AND active (power ready) DAC AND a non-48-KHz DAC sam-
ple rate and CODEC does not need a sample
5.4.2.
Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
Table 11. Status Data Port Bit Assignments
Bit
19:4
3:0
Description
Control Register Read Data
Reserved
Comments
Stuffed with 0 if tagged “invalid”
Stuffed with 0
If Slot 2 is tagged invalid by AC‘97, then the entire slot will be stuffed with 0 by AC‘97.
IDT™
40
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206