STAC9758 Datasheet, PDF (72/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
8.2.20. Extended Audio ID (28h)
Default: 0BC7h
D15
ID1
D7
SDAC
D14
ID0
D6
CDAC
D13
D12
RESERVED
D5
D4
DSA1
DSA0
D11
REV1
D3
RESERVED
D10
REV0
D2
SPDIF
D9
AMAP
D1
DRA
D8
LDAC
D0
VRA
The Extended Audio ID register is a read only register except for bits D4 and D5. ID1 and ID0 echo
the configuration of the CODEC as defined by the programming of pin 46 externally. ID0 is always a
0 for the 9758. Code 00 returned defines the CODEC as the primary CODEC, while code 10 identi-
fies the CODEC as the secondary CODEC. The AMAP bit, D9, will return a 1 indicating that the
CODEC supports the optional AC’97 2.3 compliant AC-Link slot to audio DAC mappings. The default
condition assumes that 00 are loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index
28h). With 0 in the DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specifi-
cation recommendations. If the DSA1 and DSA0 bits do not contain 0, the slot assignments are as
per the table in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will
return a 1, indicating that the CODEC supports the optional variable sample rate conversion as
defined by the AC’97 specification.
Bit
Reset R/W Name
Value
Function
15:14 00 or 10 RO
ID [1,0]
00 = XTAL_OUT grounded (note 1)
CID1#, CID0# = XTAL_OUT crystal or floating
13:12
00
RO RESERVED Bits not used; should read back 00
11:10
10
RO REV[1:0] Indicates CODEC is AC’97 Rev 2.3 compliant
9
1
RO AMAP Multi-channel slot support (Always = 1)
8
1
RO LDAC Low Frequency Effect DAC Supported
7
1
RO SDAC Surround DACs Supported
6
1
RO CDAC Center channel DAC Supported
DAC slot assignment
See DSA table below.
5:4
00
RW DSA [1,0] The DSA bits for DAC-A are ignored when Double Rate Audio DRA is
used. Slots 3&4 are used instead. The DRSS bits indicate which
secondary slots to use. DAC-B and DAC-C are unaffected by the DRA bit.
3
0
RO RESERVED Reserved
2
1
RO
SPDIF ^{0 = SPDIF pulled high on reset, SPDIF disabled}
1 = default, SPDIF enabled (Note 2)
1
1
RO
DRA Double Rate Audio Supported
0
1
RO
VRA
Variable sample rates supported (Always = 1)
Note: 1. External CID pin status (from analog) these bits are the logical inversion of the pin
polarity (pin 46). These bits are zero if XTAL_OUT is grounded with an alternate external clock
source in primary mode only. Secondary mode can either be through BIT CLK driven or 24MHz
clock driver, with XTAL_OUT floating.
Note: 2. If pin 48 is held high at powerup, register 28h (Extended Audio ID) bit [2] will be held to
zero, to indicate the SPDIF is not available. Tie pin 48 to ground with a 10 KΩ resistor to ensure
SPDIF is enabled.
IDT™
72
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206