STAC9758 Datasheet, PDF (105/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
9. LOW POWER MODES
The STAC9758/9759 is capable of operating at reduced power when no activity is required. The
state of power down is controlled by the Powerdown Register (26h). There are 7 commands of sep-
arate power down. The power down options are listed in Table 23. The first three bits, PR0..PR2,
can be used individually or in combination with each other, and control power distribution to the
ADCs, DACs and Mixer. The last analog power control bit, PR3, affects analog bias and reference
voltages, and can only be used in combination with PR1, PR2, and PR3. PR3 essentially removes
power from all analog sections of the CODEC and is generally only asserted when the CODEC will
not be needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only. PR2 and PR3
do not need to be set before a PR4, but PR0 and PR1 should be set before PR4. PR5 disables the
DSP clock and does not require an external cold reset for recovery. If PR0 and PR1 are set together,
it is the same as setting PR5. PR6 disables the headphone driver amplifier for additional analog
power saving.
Table 23. Low Power Modes
GRP Bits
PR0
PR1
PR2
PR3
PR4
PR5
PR6
Function
PCM in ADCs & Input Mux powerdown
PCM out DACs Powerdown
Analog Mixer powerdown (VREF still on)
Analog Mixer powerdown (VREF off)
Digital Interface (AC-Link) powerdown (BIT CLK forced low)
Digital Clk disable, BIT CLK still on
Powerdown HEADPHONE_OUT
Figure 20. Example of STAC9758/9759 Powerdown/Powerup Flow
PR0=1
PR1=1
PR2=1
PR4=1
Normal
ADCs off PR0 DACs off PR1
Analog off
PR2 or PR3
Digital I/F off
PR4
Shut off
AC-Link
PR0=0 & ADC=1 PR1=0 & DAC=1 PR2=0 & ANL=1
Warm Reset
Ready =1
Default
Cold Reset
The Figure 20 illustrates one example procedure to do a complete powerdown of STAC9758/9759.
From normal operation, sequential writes to the Powerdown Register are performed to power down
STAC9758/9759 a section at a time. After everything has been shut off, a final write (of PR4) can be
executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding
their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line,
issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9758/9759 can
also be woken up with a cold reset. A cold reset will reset all of the registers to their default states
(Paged Registers are semi-exempt). When a section is powered back on, the Powerdown Control/
Status register (index 26h) should be read to verify that the section is ready (stable) before attempt-
ing any operation that requires it.
IDT™
105
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
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