STAC9758 Datasheet, PDF (92/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
8.6.9.
I/O Misc. (68h, Page 00h)
Register 24h must be set to Page 00h to access this register.
Default: 2001h
D15
NOBLKCHK
D7
P48 MO
D14
SPIS A1
D6
P47 M1
D13
SPIS A0
D5
P47 M0
D12
D11
SPI_SELEN1 SPI_SELEN0
D4
D3
DCS
DBS
D10
VI
D2
DAS
D9
AMute
D1
HP SELEN1
D8
HP3dB
D0
HP SELEN0
Bit(s) Reset Value R/W
Name
Description
0 = normal behavior
15
0
RW
NOBLKCHK
1 = disable block size checking for SPDIF_IN.
This is needed primarily for testing so short blocks can be sent to
result in quicker PLL_LOCKED assertion.
SPDIF_IN slot select
14:13
01
RW SPISA<1:0> 00 = Slots 3/4
10 = Slots 6/9
01 = Slots 7/8
11 = Slots 10/11
12:11
00
RW SPI SELEN <1:0> SPDIF_IN Select and Enable
00 = SPDIF Input powered down
01 = SPDIF Input to AC LINK
10 = SPDIF Input to DAC 2
11 = SPDIF Input to both ACLINK and DAC 2
10
0
RW
VI
0 = Respond to SPDIF_IN valid tag
1 = Ignore SPDIF_IN valid tag
9
0
RW AMUTE Disable 0 = Auto mute when SPDIF stream marked non PCM
1 = Auto Mute disabled.
8
0
RW
HP3dB
HEADPHONE +3dB Boost
0 = 3dB off
1 = 3dB on
7
0
RW
P48 M0
Pin 48 configuration
0 = SPDIF OUT
1 = ADAT OUT
6:5
00
RW P47 M1:M0 Pin 47 configuration
00 = EAPD output/GPIO
01 = No Function
10 = SPDIF Input (special buffer for low level signals)
11 = SPDIF Input (standard input for high level signals)
4
0
RW
DCS
DAC-C channel Swap
0 = Normal operation
1 = Center and LFE swapped
3
0
RW
DBS
DAC-B channel Swap
0 = Normal operation
1 = Left and Right swapped
IDT™
92
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206