STAC9758 Datasheet, PDF (32/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
Table 4. AC-Link Output Slots (Transmitted from the Controller)
Slot
Name
Description
A. 20-bit PCM data for SPDIF Left Channel
10
4 different uses
B. extra slots for Double Rate Audio for DAC-A
C. extra slots for Double Rate SPDIF
C. Modem Line2 DAC
A. 20-bit PCM data for SPDIF Right Channel
11
4 different uses
B. extra slots for Double Rate Audio for DAC-A
C. extra slots for Double Rate SPDIF
D. Modem handset DAC
12
Modem IO control
GPIO write port for modem Control
12
CODEC IRQ
Can be used by CODEC if a modem CODEC is not
present.
Table 5. The AC-Link Input Slots (Transmitted from the CODEC)
Slot
Name
Description
0
SDATA_IN TAG
MSBs indicate which slots contain valid data
1 STATUS ADDR read port MSBs echo register address; LSBs indicate which slots request data
2 STATUS DATA read port 16-bit command register read data
3, 4 PCM L&R ADC record 20-bit PCM data from Left and Right inputs
5
Modem Line 1 ADC not used by STAC9758/9759
6-11
PCM ADC Record
20-bit PCM data - Alternative Slots for Input
12
GPIO Status
GPIO read port and interrupt status
5.2.
AC-Link Serial Interface Protocol
The AC‘97 Controller signals synchronization of all AC-Link data transactions. The AC‘97 CODEC,
Controller, or external clock source drives the serial bit clock onto AC-Link, which the AC‘97 Control-
ler then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 KHz, is
derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the
necessary clocking granularity to support 12 20-bit outgoing and incoming time slots. AC-Link serial
data is transitioned on each rising edge of BIT_CLK. The receiver of AC-Link data (CODEC for out-
going data and Controller for incoming data) samples each serial bit on the falling edges of
BIT_CLK.
The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid
tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0
indicates that the corresponding time slot within the current audio frame has been assigned to a data
stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the
data, (AC‘97 CODEC for the input stream, AC‘97 Controller for the output stream), to stuff all bit
positions with 0 during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The
portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the
audio frame where SYNC is low is defined as the “Data Phase”.
Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that an
AC‘97 CODEC be implemented as a static design to allow its register contents to remain intact when
entering a power savings mode.
IDT™
32
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
V 1.2 1206