STAC9758 Datasheet, PDF(39/119 Page) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

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STAC9758 Datasheet, PDF (39/119 Pages) Integrated Device Technology – HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS

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STAC9758/9759

HIGH-PERFORMANCE 6-CHANNEL ACâ97 2.3 CODEC WITH UNIVERSAL JACKSâ¢

PC AUDIO

5.4.1.

Slot 0: TAG

Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the ACâ97

CODEC is in the âCODEC Readyâ state or not. If the âCODEC Readyâ bit is a 0, this indicates that

the ACâ97 CODEC is not ready for normal operation. This condition is normal following the deasser-

tion of power-on-reset for example, while the ACâ97 CODECâs voltage references settle. When the

AC-Link âCODEC Readyâ indicator bit is a 1, it indicates that the AC-Link and ACâ97 CODEC control

and status registers are in a fully operational state. CODEC must assert âCODEC Readyâ within

400 Âµs after it starts receiving valid SYNC pulses from the controller, to provide an indication of con-

nection to the link and that Control/Status registers are available for access. The AC`97 Controller

and related software must wait until all of the lower four bits of the Control/Status Register, 26h, are

set before attempting any register writes, or attempting to enable any audio stream, to avoid undesir-

able audio artifacts.

Prior to any attempts at putting an ACâ97 CODEC into operation the ACâ97 Controller should poll the

first bit in the AC-Link input frame (SDATA_IN slot 0, bit 15) for an indication that CODEC has gone

âCODEC Readyâ. Once an ACâ97 CODEC is sampled âCODEC Readyâ1 then the next 12 bit posi-

tions sampled by the ACâ97 Controller indicate which of the corresponding 12 time slots are

assigned to input data streams, and that they contain valid data.

5.4.1.1. Slot 1: Status Address Port / SLOTREQ Signaling Bits

Table 9. Input Slot 1 Bit Definitions

Bit

18-12

1, 0

Description

RESERVED (Set to 0)

Control Register Index Echo (Set to all 0 if tagged âinvalidâ by ACâ97 CODEC.)

On Demand Data Request Flags for slots 11-2 (next output frame):

0 = send data

1 = do NOT send data

Slot 3 request: PCM Left channel

Slot 4 request: PCM Right channel

Slot 5 request: RESERVED

Slot 6 request: PCM Center

Slot 7 request: PCM Left Surround

Slot 8 request: PCM Right Surround

Slot 9 request: PCM LFE

Slot 10 request: SPDIF

Slot 11 request: SPDIF

Slot 12 request: Interrupt Status and GPIO

RESERVED (Set to 0)

Note: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

1. There are several subsections within an ACâ97 CODEC that can independently go busy/ready. It is the responsibility of the

ACâ97 Controller to probe more deeply into the ACâ97 CODECâs register file to determine which subsections are actually ready.

(See section 8.5. for Extended CODEC Registers Page Structure Definition, on page 85 for more information.)

IDTâ¢

HIGH-PERFORMANCE 6-CHANNEL ACâ97 2.3 CODEC WITH UNIVERSAL JACKSâ¢

STAC9758/9759

V 1.2 1206

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