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IC-PVL Datasheet, PDF (9/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER
iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
Rev B3, Page 9/33
OPERATING REQUIREMENTS: Serial and Parallel Interface
Operating conditions:
VDD = 3.0...5.5 V, VBAT < VDD + 1.0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.
Item Symbol Parameter
No.
Conditions
Min.
Max.
Serial Interface Mode (SSI or Chain Mode if Applicable)
I001
I002
I003
I004
I005
I006
I007
twait
treq
tC
fC
tL1
tL2
tframe
SSI Request after VDD Power-on
Request Signal lo Level Duration
Permissible Clock Period
Permissible Clock Frequency
Clock Signal hi Level Duration
Clock Signal lo Level Duration
Cyclic Multiturn Data Frame Request
Interval
due to Elec. Char. B02
due to Elec. Char. B02
10
50
0.25
1/(2·tout )
50
50
85
2·tout
10
I008 tS
Setup Time:
refer to Fig. 2
30
Data stable before clock edge hi → lo
I009 tH
Hold Time:
refer to Fig. 2
30
Data stable after clock edge hi → lo
I2C Slave Mode Direct Access
I010 twait
I011 fscl
I2C Request after VDD Power-on
10
Permissible Input Clock Frequency
I2C standard mode with timeout Elec. Char.
1/(2·tout )
100
B02
Parallel Encoder Mode (SEL = High)
I012 tstart
Length of Start Pulse on PRE Pin
see Figure 11 on Page 21
1
I013 tcycle
Time Between Two Consecutive Sensor see Figure 11 on Page 21
30
Read Cycles
Unit
µs
ns
µs
MHz
ns
ns
µs
ns
ns
µs
kHz
µs
µs
t
frame
t
t tt
t
t
req
c
L1 L2
p
out
CLK
REQ
DO
MT MSB
...
MT LSB PCR 7
...
PCR 0 Sync 2 Sync 1 Sync 0 NERR NWRN PARITY
Absolute Data Multiturn
(Period Count per Revolution)
(Synchronization)
(Error + Warning)
(Parity)
Timeout
Figure 1: I/O line signals of the serial interface in SSI mode (INT_MODE = 0)
NSL
tt
SH
t
c
to iC-LNB/LNG only
DI
ST MSB
MSB-1
...
ST LSB DIN
DIN
CLK
DO
MT MSB MSB-1 MSB-2
...
MT LSB ST MSB
…
ST LSB DIN
DIN
t
p
t
frame
t
out
Sample ST MSB
for synchronisation
(first CLK rising edge)
Figure 2: I/O line signals of the serial interface in chain mode (INT_MODE = 1).