IC-PVL Datasheet, PDF (28/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
APPLICATION EXAMPLES: Singleturn iCs with multiturn interface (SSI Mode)
Rev B3, Page 28/33
1uF
100nF
PRESET
SCL
SDA
DI_P1
SEL
PRE
iC-PVL
VBAT
Supply Switch
VDD
Monitor
I²C
MultiMaster
or Slave
RAM
Config
Logic + Serial Interface
SSI Interface
Serial/
Parallel
Output
Position Encode
Operating Mode Selection
Hall Control
+- _{1 1 0} 0 _{1 1}
Multiturn Counter
FlexCount
Error
Monitor
Oscillator
-
B
+
B
B
-
B
+
Hall Sensor Line
GND
SIN
DIG
SIN/DIG Converter
VDDS
DO_P0
N0
CLK_N1
NERR
NWRN
P2
N2
SDA
SCL
SDA SCL VDD
EEPROM
100nF
GND
Incremental
(optional)
A
B
Z
VPA
VPD
iC-MU
MTD
Multiturn
Interface
MTC
Amplitude
Control
+ PGA
Clock
Bias
Reference
Configuration
128 Byte RAM
Synchronization
Interface Handler
Error Management
Encoder Processor
I2C EEPROM
Interface
SCL
SDA
Port B
PB0
PB1
PB2
NERR
ANA/DIG Output
Master Track
B
Nonius Track
B
Hall Sensors
VNA
12 Bit
12 Bit
Sine/Digital
VND
Port A
PA0
PA1
PA2
PA3
Ser Interface
Serial
Interface
BiSS
SSi
SPI
Figure 13: Principle application example. iC-PVL as battery-buffered multiturn device connected to the MT in-
terface of the iC-MU absolute singleturn encoder. Interface operating in SSI-Mode (INT_MODE =
0). The two iCs share one common EEPROM for configuration. BiSS register access via iC-MU
is used for access to iC-PVL STATUS register, for iC-PVL COMMAND execution (e.g. REBOOT,
SCLR, SLEEP), and for EEPROM access (iC-PVL configuration). BiSS, SPI or SSI are available
for serial data transmission (refer to iC-MU datasheet for details).
VDD
iC-SM2L ^VB
GND
PSIN
NSIN
PCOS
NCOS
VACO VDDA
VDD VBAT
VBATS
ACOM
ACOS
ACON
Battery Switch
Reverse
Polarity
Protection
PCOUT
NCOUT
PSOUT
NSOUT
PSINM
NSINM
PCINM
NCINM
PSINS
NSINS
NERR
Error MNFOK
iC-MNF ^Monitor
SLO
NSLO
MA
I/O
NMA
SLI
MAO
PCINS
NCINS
SDA
I2C
SCL
PSINN
NSINN
MTSLI
MT
MTMA
PCINN
NCINN
EP1 EP2
GNDA GND
RES
Preset
& Test
DIR
PRES
T3 T1 T0
optional
LED
LED
Analog out +
Calibration Signals
PCOUT
VDD
NCOUT
PSOUT
NSOUT
EEPROM
SDA SCL
GND
MNFOK
SLO
NSLO
MA
NMA
SLI
BiSS Interface
100nF
SDA SCL
VDD
100nF
VDDS
Monitor
1uF
VBAT
Supply Switch
iC-PVL
RES
DIR
PRES
optional battery warning
to MNF GPIO EP2
optional preset iC-PVL
via MNF GPIO EP1
Calibration Signals
T0
T1
DO_P0
N0
CLK_N1
NERR
NWRN
I2C
Multi
Maosrter
Slave
RAM
Config
SERIAL or
PARALLEL
OUTPUT
Error
Monitor
1 0 0 1 1 ^+-
Multiturn
Counter
Logic and Serial Interface
SSI Interface
Position Encode
Operating Mode Selection
Hall Control
P2
SIN
N2
DIG
GND
SIN/DIG Converter
-
B
+
B
-
B
+
B
Hall Sensor Line
Oscillator
DI_P1
PRE
SEL
PRESET
GND
Figure 14: Principle application example. iC-PVL as battery-buffered multiturn device connected to the MT
interface of the iC-MNF nonius encoder (together with an iC-SM2L AMR linear position sensor).
iC-PVL interface is operated in SSI-Mode (INT_MODE = 0). The two iCs share one common
EEPROM for configuration. BiSS register access via iC-MNF is used for access to iC-PVL
STATUS register, for iC-PVL COMMAND execution (e.g. REBOOT, SCLR, SLEEP), and for
EEPROM access (iC-PVL configuration). BiSS or SSI are available for serial data transmission
(refer to iC-MNF/iC-SM2L datasheet for details).