IC-PVL Datasheet, PDF (10/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
CONFIGURATION PARAMETERS
Rev B3, Page 10/33
Hall Sensor Signal Conditioning
DIR:
Code Direction (P. 18)
OS:
Electrical Offset Multiturn to Singleturn
(P. 18)
Serial Interface
INT_MODE: Serial Interface Operating Mode (P. 19)
MT_GRAY: Multiturn Output Data Format (P. 19)
ST_GRAY: Singleturn Input Data Format (P. 19)
MT_BW: Bit Width of Multiturn Data and Counter
(P. 19)
SYNC_BW: Synchronization Bit Width (P. 20)
PCR:
Period Count per Revolution (P. 17)
PCR_OUT: PCR Output Mode (P. 17)
EN_ERR: Error Bit Transmission Enable (P. 20)
EN_PAR: Parity Bit Transmission Enable (P. 20)
Bias and Oscillators
IBIAS:
Bias Current; Oscillator Frequency
Calibration (P. 27)
A_MAX: Maximum Angle Acceleration (P. 26)
Battery Monitor
BAT_MON: Battery Monitoring Enable (P. 25)
EN_WRN: Low Battery Warning Enable (P. 20)
BAT_THR: Battery Monitor Thresholds (P. 25)
Miscellaneous
POLEWID: Pole Size of Magnetic Scale (P. 16)
ONAX:
On-Axis Magnetic Scanning (P. 17)
ABQUAD: AB Quadrature Output (P. 20)
HYS:
Hysteresis (P. 20)
I2C_POS: Enable I²C Position Read-out (P. 23)
MT_PREL: Multiturn Counter Preload Value (P. 21)
CHIP_REL: Chip Release (P. 23)
CRC Checksums
CRC_CFG: Checksum for Chip Configuration
(0x00-0x05) (P. 22)
CRC_CTR: Checksum for MT_PREL (0x07-0x0B)
(P. 22)
REGISTER MAP (EEPROM)
OVERVIEW
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Interface and Hall Signal Processing
0x00
EN_PAR
EN_ERR
DIR
ST_GRAY
0x01
OS
MT_BW
0x02
PCR
Battery Monitor, Bias and Oscillators
0x03
EN_WRN BAT_MON
A_MAX
Miscellaneous
0x04
0
0
0
0
0
ONAX
0x05
I2C_POS
PCR_OUT
SYNC_BW
BAT_THR
CRC Configuration (inverted)
0x06
CRC_CFG(7:0)
Multiturn Counter: Preload Value
0x07
MT_PREL(7:0)
0x08
MT_PREL(15:8)
0x09
MT_PREL(23:16)
0x0A
MT_PREL(31:24)
0x0B
MT_PREL(39:32)
CRC Counter (inverted)
0x0C
CRC_CTR(7:0)
Bit 1
Bit 0
MT_GRAY INT_MODE
IBIAS
POLEWID
HYS
ABQUAD
Table 5: Register map