IC-PVL Datasheet, PDF (24/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
Rev B3, Page 24/33
dervoltage considerably lower than the battery error
threshold. Another reason may be due to insufficient
stabilizing capacitors at the supply lines VDD and VBAT.
PRESET: Pin Preset Detected
As described on Page 14, a preset pulse at pin PRE
is mandatory to initialize and boot-up the iC-PVL after
battery insertion. Therefore, this bit is set after each
startup. It may be reset by overwriting it or issuing a
reset instruction. This can be interpreted as an acknowl-
edgment that this startup was intentional. If the bit is set
later during field operation, it is most likely unintentional.
The cause may have been an external disruption or
short circuit error on the PRE line.
STATUS
Bit
0
1
2
3
4
5
6
7
Addr. 0x10; bit 7:0
Name
Description
STUP_ERR Startup error
CFG_ERR
Internal configuration error
CTR_ERR
Internal counter error
POS_ERR
Position error
BAT_ERR
Battery error
BAT_WRN
Battery early warning
PDR
Power down reset detected
PRESET
Pin preset detected,
I²C REBOOT detected,
Sleep mode activated
Table 29: Status byte
Command Register
The RESET command reinitializes the internal circuitry.
Counter position and configuration remain untouched.
Error Output NERR
An LED may be connected to the error output NERR to
signalize errors. The pin is an open drain output driver.
If an error is detected, the pin is pulled low. STUP_ERR,
CFG_ERR, CTR_ERR, POS_ERR, BAT_ERR are visi-
ble at NERR.
CMD
Code
0x00
0x01
0x02
0x03
0x04
0x05
...
Addr. 0x11; bit 7:0
Name
Description
none
Reserved
none
Reserved
RESET
Soft reset
REBOOT
Reboot and preset from EEPROM
SLEEP
Halt iC-PVL position sensing
SCLR
Clear all status bits
none
No operation
Error Output During Startup
During startup phase, a low level at NERR is visible.
I.e., from preset pulse until complete and correct config-
uration read-in from the EEPROM. This indicates that
iC-PVL is not ready to operate yet and does not answer
a position read request. A reader must wait until error
indication is cleared after successful boot-up.
Warning Output NWRN
Battery early warning BAT_WRN is exclusively output
at open drain pin NWRN.
Status Byte
Table 29 gives a summary of available error and status
messages. Errors can be acknowledged by overwriting
the status byte at the desired position or by sending
the SCLR command. If the error is still active, iC-PVL
error monitor will set it again immediately, i.e, the error
condition is still present.
Table 30: Command register
The REBOOT command reinitializes the internal cir-
cuitry, reloads new configuration and counter preload
value from EEPROM. The same actions are performed
after a preset pulse at pin PRE.
The SLEEP command stops all position sensing action
during battery mode and VDD mode. No position is
tracked anymore. Power consumption is reduced to a
minimum but interfaces are active during VDD supply.
This is useful for the storage of encoders with installed
battery.
Sleep mode is skipped and position tracking is restarted
on any I2C write instruction. Read instructions like sta-
tus read do not skip sleep mode. With activation of
the sleep mode, the status bit 7 (PRESET) is activated
and an error is indicated at pin NERR. After leaving the
sleep mode, NERR indication is removed and a SCLR
command can be used to reset the status bit 7.
The SCLR command (Status CLeaR) is used to clear
all status messaged in the status register.