IC-PVL Datasheet, PDF (20/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
Rev B3, Page 20/33
SYNC_BW
Code
00
01
10
11
Addr. 0x05; bit 1:0
Bit width Tolerable phase shift range
0 bit
no synchronization bit
1 bit
0 ° ... 180 °
2 bit
0 ° ... 270 °
3 bit
0 ° ... 315 °
Table 20: Synchronization bit width and resulting toler-
able ideal phase shift
After the transmission of the absolute position and the
synchronization information, iC-PVL’s serial protocol al-
lows the optional transmission of an error bit, a warning
bit and a parity bit.
The error bit signalizes if a startup error, a wrong CRC
checksum, an empty battery or position error (e.g. over-
speed or magnet loss). Its polarity is configured with
parameter EN_ERR shown in Table 21.
The warning bit represents an early battery warning.
It indicates a low battery while the system is still func-
tional. The polarity of the warning bit follows the polarity
configured with EN_ERR. Details regarding error and
status information are explained on Page 23. The op-
tional parity bit finishes the transmission. Its polarity is
either even or odd according to parameter EN_PAR.
Finally, the last 8 LSBs of the multiturn data can be
used to transmit the period counts revolution in off-axis
applications. See Table 11 for details.
The line signals for both interface modes are shown in
Figures 1 and 2 on Page 9. Optional bits are greyed-out.
The number of transmitted multiturn and singleturn bits
depends on parameter MT_BW and ST_BW.
EN_ERR
Code
00
01
10
11
Addr. 0x00; bit 5:4
Mode
Communication without error bit
Calibration mode
Communication with additional error bit
(negative polarity)
Communication with additional error bit
(positive polarity)
Table 21: Error bit enable
EN_WRN
Code
0
1
Addr. 0x03; bit 7
Mode
Communication without warning bit
Communication with additional warning bit
(polarity as configured via EN_ERR)
Table 22: Warning bit enable
EN_PAR
Code
00
01
10
11
Addr. 0x00; bit 7:6
Mode
Communication without parity bit
reserved
Communication with additional parity bit
(even polarity)
Communication with additional parity bit
(odd polarity)
Table 23: Parity bit enable
OUTPUTS N0, P2, N2
In serial interface (P. ) or I²C slave mode (P. ), the out-
puts N0, P2, N2 provide either parallel or incremental
position information. A magnetic period is divided in
eight sectors. By default, these three bits are output in
real-time at N0, P2, N2.
ABQUAD
Addr. 0x05; bit 0
C. Mode
N2
P2
N0
0 Parallel position MSB
MSB-1
LSB
1 Quadrature AB B
A
none
N. The output is inverted to the internally generated position.
Table 24: AB quadrature output
With configuration parameter ABQUAD, a quadrature
output can be activated. In this mode, A and B are
output at P2 and N2. One magnetic period is interpo-
lated by a factor of two, i.e., two quadrature periods are
observed per period corresponding to eight countable
edges per period.
For evaluating these outputs, a hysteresis may be de-
sired. Configuration parameter HYS activates a hys-
teresis of 45°.When active, the synchronization bits of
the serial data output also feature a 45° hysteresis.
HYS
Code
0
1
Addr. 0x05; bit 1
Mode
No angle hysteresis
45° hysteresis on direction change
Table 25: Angle hysteresis