IC-PVL Datasheet, PDF (22/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
I²C MULTIMASTER INTERFACE AND CRC PROTECTION
Rev B3, Page 22/33
Pins SCL and SDA form an interface to read an ex-
ternal EEPROM according to the I²C protocol (with at
least 128 bytes, e.g. 24C01, 24C02, 24C08 and maxi-
mum 24C16, extended address range is not supported).
Writing to the EEPROM is not supported.
By default, this EEPROM is used to store the iC-PVL
configuration (at addresses 0x00 to 0x0C) according
to the register map on Page 10. The configuration is
protected against bit errors by an 8-bit CRC checksum.
A checksum failure is displayed at output NERR and
via the error bit at the end of the SSI data. The multiturn
counter preload value is stored in its own configura-
tion area (0x07 - 0x0B) and is also saved with its own
CRC on 0x0C. The CRC of the remaining four config-
uration bytes (0x00 - 0x05) is stored at address 0x06.
Both CRC checksums are generated with the polyno-
mial X⁸ +X⁵ +X³ +X² +X¹ +1 (0x2F, also named 0x12F
sometimes). The CRC start value is zero.
Note: In order to avoid an EEPROM content of all
bytes = 0x00 to be a valid configuration, the CRC check-
sums in addresses 0x06 and 0x0C are stored inverted .
Since iC-PVL does only read configuration data, writing
EEPROM requires an external programming via pins
SCL and SDA (I²C protocol). Refer to circuit on Page
29. In applications with a shared EEPROM, e.g. with
iC-MU or iC-MHM, the EEPROM programming of the
iC-PVL configuration can be done via the BiSS interface
of the singleturn IC.
If no EEPROM is available or desired in the application,
programming the iC-PVL by a microcontroller (MCU) is
possible. As described in the subsequent chapter, the
I²C slave mode allows direct read/write access to inter-
nal configuration and counter. Alternatively, the MCU
may emulate an EEPROM (i.e. an I²C slave), since
iC-PVL is acting as a bus master by default. At startup,
after a short high pulse at pin PRE, the iC-PVL requests
addresses 0x00 to 0x0C from the connected I²C slave.
This is done in a combined write/read command as
shown in Figure 12, repeating 13 times.
The expected slave address here is 0xA0 or
"0b 1010 000", the standard I²C EEPROM address.
Notes: In typical applications, the iC-PVL is used in
combination with external encoder, line driver or safety
ICs. If several devices try to share one common EEP-
ROM, the default configuration area of iC-PVL may
not be usable (addresses 0x00 to 0x0C).
Therefore, the iC-PVL is capable to boot from dif-
ferent addresses. The EEPROM is scanned for the
unique iC-PVL configuration footprint, i.e. 13 bytes
with correct checksums of configuration and counter
preload. If no configuration is found at address 0x00
to 0x0C, the iC-PVL searches at address 0x40 to
0x4C, then at address 0x80 to 0x8C and finally at
address 0xA0 to 0xAC.
f
scl
SCL
latch counter
after Read bit
SDA
S 1 0 1 0 A2 A1 A0 W ACK D7 ... D0 ACK Sr
S 1 0 1 0 A2 A1 A0 R ACK D7 … D0 ACK P
Start
cond.
Claiming
the bus
Slave Address (7 bit “1010000“)
Write ACK
(Slave)
Data (8 bit)
EEPROM
address
to read
Master requesting the address to read
(write command master to slave)
ACK Start
(Slave) repeated
condition
Keeping
the bus
Slave Address (7 bit “1010000“)
Read ACK
(Slave)
Data (8 bit)
read from
requested
address
Master reading the data at requested address
(read command master to slave)
NACK Stop
(Master) cond.
Releasing
the bus
Figure 12: iC-PVL combined write/read command reading one slave address