IC-PVL Datasheet, PDF (23/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
I²C SLAVE MODE
Rev B3, Page 23/33
Additionally to the I²C master interface described in the
previous section, iC-PVL can be booted as I²C slave
(see circuit of Figure 4 on page 12).
At I²C device ID = 0b1100 001 iC-PVL’s internal regis-
ters are addressed according to the register map on
page 11.
The I²C communication protocol described in Figure 12
may be used for read and write register access. The
internal multiturn counter is readable at address 0x07 to
0x0B, protected with CRC checksum at address 0x0C.
Additionally, the three synchronization bits are readable
at address 0x0D.
Note: For a consistent position information, it is nec-
essary to read all these position registers in one burst
command. The counter and synchronization bits are
latched after each read addressing (i.e. read/not write
bit = high). At burst command, the addressing for read
is done only once, for the first address 0x07. The
effective clock edge is marked in Figure 12.
If the seven registers are read in seven separate read
instructions, the transmitted position may change dur-
ing readout time and the transmitted position will be
inconsistent.
Access to the internal counter via I²C needs to be en-
abled with configuration parameter I2C_POS. This bit
locks position read-out to SSI or I²C exclusively.
I2C_POS
Code
0
1
Addr. 0x05; bit 7
Function
SSI read-out of MT counter only
I²C read-out of MT counter only
Table 27: Enable I²C or SSI position read-out
For chip release verification purposes an identification
value is stored under ROM address 0x0F; a write ac-
cess to this address is not permitted.
CHIP_REL
Code
0x01
0x02
0x03
0x04
Note
Adr 0x0F, bit 7:0 (ROM)
Chip Release
iC-PVL Y
iC-PVL Y1
iC-PVL X
iC-PVL X1
For all previous versions, address 0x0F is not
readable via I2C or answer is 0x00.
Table 28: Chip Release
ERROR MONITOR, STATUS AND COMMAND REGISTER
The iC-PVL has several error conditions. These are
stored in a status byte which is readable at I²C address
0x10.
STUP_ERR: Startup Error
Erroneous startup procedure, e.g., I²C stuck-at, EEP-
ROM read error or invalid CRC checksum stored in
the EEPROM. No position acquisition is performed. In-
terfaces are blocked. Please revise configuration and
checksums or replace EEPROM. Reboot iC-PVL.
CFG_ERR: Internal Configuration Error
The configuration stored in the internal RAM had an un-
expected level flip of one or more bits, visible as wrong
CRC checksum. Position is invalid. Reboot iC-PVL.
CTR_ERR: Internal Counter Error
The internal period counter had an unexpected level flip
of one or more bits, visible as wrong CRC checksum.
Position is invalid. Reboot iC-PVL.
tion jump, caused e.g. by excessive speed or excessive
acceleration of the magnetic disc or tape. Alternatively,
this error bit is set on weak, disturbed magnetic sig-
nals or complete loss of magnet. Position is invalid.
Optimize magnet position and cross-check angular ve-
locity/acceleration with Table 33. Reboot iC-PVL.
BAT_ERR: Battery Error
Battery undervoltage according to Elec. Char. No. 404.
Position is invalid. Change battery. Reboot iC-PVL.
Battery monitoring is active during VDD supply.
BAT_WRN: Battery Early Warning
Battery voltage early warning according to Elec. Char.
No. 405. Battery may be changed during main supply
(VDD) as soon as possible. Alternatively, halt system,
read current position and restore it. Switch off system,
change battery and restart. Restored position may be
set as counter preload. Battery monitoring is active
during VDD supply.
POS_ERR: Position Error
PDR: Power Down Reset Detected
The position encoding observed an unexpected posi- A power down reset was performed, caused by un-