IC-PVL Datasheet, PDF (4/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
PACKAGING INFORMATION
Rev B3, Page 4/33
PIN CONFIGURATION
QFN16 4 mm x 4 mm (top view)
16 15 14 13
1
2
3
<P-CODE>
<A-CODE>
4
<D-CODE>
5678
PIN FUNCTIONS
No. Name Function
1 SEL
Mode Select Input¹⁾
Low: Battery buffered counter with serial read-out
High: 3 bit parallel complementary output
Shorted to PRE input : I²C slave mode
2 PRE Preset Trigger Input
3 NERR Error Output (active low)
4 SDA I²C Interface, Data Line
5 GND Ground
12 _{6 VBAT Battery Supply Voltage Input}
(typ. 3.6 V)
7 VDDS Switched Supply Voltage Output
11
8 VDD +3.0 V to 5.5 V Main Supply Voltage
Input
9 N2
10
Parallel Output Bit 2 (negative logic),
Incremental Output B
10 P2
Parallel Output Bit 2 (positive logic),
9 _{11 N0}
Incremental Output A
Parallel Output Bit 0 (negative logic)
12 NWRN Battery Warning Output (active low)
13 DO_P0 Multiturn Interface, Data Output,
Parallel Output Bit 0 (positive logic)
14 CLK_N1 Multiturn Interface, Clock Line,
Parallel Output Bit 1 (negative logic)
15 DI_P1 Multiturn Interface, Data Input,
Parallel Output Bit 1 (positive logic)
16 SCL I²C Interface, Clock Line
BP
Backside paddle ²⁾
IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes);
1) Do not leave pin open.
2) Connecting the backside paddle is recommended by a single link to GND. A current flow across the paddle is not permissible.