IC-PVL Datasheet, PDF (18/33 Pages) IC-Haus GmbH – LINEAR/OFF-AXIS BATTERY-BUFFERED HALL MULTITURN ENCODER

iC-PVL LINEAR/OFF-AXIS
preliminary
BATTERY-BUFFERED HALL MULTITURN ENCODER
COMPENSATION OF ASSEMBLY: Data Offset and Counting Direction
Rev B3, Page 18/33
Assembled together with a magnetic code disc, code
wheel or magnetic tape, the integrated Hall sensor
signal processing generates a three bit position word,
i.e. eight positions per magnetic period. Therefore, the
iC-PVL provides up to three synchronization bits to the
singleturn sensor in SSI read-out mode.
The position can be electrically manipulated to achieve
the desired (leading or trailing) phase shift, regardless
of the actual mounting position. This is useful if the
phase relationship between an additional singleturn iC
and the iC-PVL as multiturn encoder is unknown, or
the singleturn sensor takes care of the synchronization
(SSI mode) and expects a defined phase relationship.
An offset value is added to the digitized Hall sensor
position according to parameter OS (see Table 13).
OS
Code
000
001
010
011
100
101
110
111
Addr. 0x01; bit 7:5
Phase shift
0 °, no shift
+ 45 ° leading
+ 90 ° leading
+ 135 ° leading
± 180 ° leading or trailing
- 135 ° trailing
- 90 ° trailing
- 45 ° trailing
Table 13: Offset multiturn to singleturn
Note: 0 ° to 180 ° is the ideal range for tolerated val-
ues of phase shift between ST and MT. This range is
further reduced due to communication, propagation or
processing delays for the specific application. Typically,
it is reduced by a few degrees, but increases with the
signal frequency.
In applications where the chain operation mode is used
(see Page 19), the iC-PVL takes care of synchroniza-
tion. Therefore, it has to be mounted in a leading po-
sition in relation to the singleturn iC. If the mounting
position varies from that, the OS parameter can be
used to achieve this phase shift. To ensure correct
synchronization of multiturn and singleturn data, the re-
sulting phase shift between the multiturn and singleturn
position must be within the range of 0 ° to 180 ° (MT
leading).
DIR
Code
0
1
Addr. 0x00; bit 3
Code direction
Normal
Inverted
Table 14: Code direction
The counting direction can be easily swapped with the
configuration bit DIR. The bit would be typically used to
invert the counting direction if the iC-PVL is assembled
rotated or flipped.