IC-MD_17 Datasheet, PDF (8/30 Pages) IC-Haus GmbH – 48-BIT QUADRATURE COUNTER

iC-MD 48-BIT QUADRATURE COUNTE^pR^reliminary
WITH RS422 RECEIVER AND SPI/BISS INTERFACE
Rev B1, Page 8/30
OPERATING REQUIREMENTS: BiSS and SSI Interface
Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 °C, unless otherwise noted; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item Symbol Parameter
No.
Conditions
Min.
Unit
Max.
SSI Output (ENSSI = 1)
I101 T_MAS
Permissible Clock Period
ENSSI = 1
SLI = open
250
2x t_tos
ns
I102 t_MASh
Clock Signal Hi Level Duration
I103 t_MASl
Clock Signal Lo Level Duration
BiSS C Single Cycle Data
25
t_tos
ns
25
t_tos
ns
I104
I105
I106
T_MAS
t_MASh
t_MASl
Permissible Clock Period
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
ENSSI = 0
100
ns
25
t_tos
ns
25
ns
Figure 2: Timing diagram of SSI output.
Figure 3: Timing diagram of BiSS C DATA (here: CDS, counter data, status, CRC)